FIG. 1 shows a general depiction of a continuous-time delta sigma (ΔΣ) analog-to-digital converter (ADC). The conventional ΔΣ ADC converts an analog input signal u into a high-frequency serial bit sequence having a low resolution, often only 1 bit (0 or 1), here called vd. This coarsely quantized bit sequence vd is converted into a highly accurate digital signal w with a lower sampling rate through subsequent digital low pass decimation filters, Hd. This is possible since the energy of the quantization noise is distributed at frequencies outside the frequency band of interest.
The ΔΣ ADC of FIG. 1 comprises a coarse quantizer, a loop filter and a feedback DAC. The coarse quantizer comprises one or more comparators clocked at a clock rate a lot higher than the bandwidth of the analog input signal u. The digital-to-analog converter (DAC) provided in the feedback branch generates from the digital output signal of the quantizer, vd, a sequence of quantized analog signals here called the feedback signal, va. The loop filter processes both the analog input signal u and the quantization errors, ε, injected into the system in the coarse quantizer. By selecting the transfer function of the loop filter, Lu and Lv, in such a way that, in the band of interest, the transfer function for the quantization errors c is many times smaller than the transfer function for the analog input signal u, the signal-to-quantization “noise” ratio (SQNR) in that particular frequency band can be made large.
Thus, by selecting Lv properly, the noise transfer function (NTF) can be made high-pass or band-pass:
                    NTF        =                                            v              d                        ɛ                    =                      1                          1              -                              L                v                                                                        (        1        )            
whereas the signal transfer function (STF) is a function of both Lu and Lv:
                    STF        =                                            v              d                        u                    =                                    L              u                                      1              -                              L                v                                                                        (        2        )            
The loop filter can be implemented using active discrete time (DT) filters or active continuous time (CT) filters or even passive loop filters. If the NTF is selected having zeros at low frequencies (DC), the loop filter will be built up of integrators, which can be implemented using negative feedback amplifiers. The reason for using CT filters above their DT counterparts is that they provide anti-alias filtering, have no front-end sampling, no kT/C noise and theoretical speed advantages which lead to a lower power consumption at a given analog signal bandwidth.
Prior art in the implementation of the feedback DAC in CT modulators is to use a switched current (SI), or a switched capacitor (SC) to inject a well defined amount of charge to the summing node of the integrator.
FIG. 2 shows a possible implementation of a 1-bit SI feedback according to prior art. A logically high data bit of the digital output signal (HIGH), vd, is applied as a corresponding reference voltage (for example VREF+=1 volt) to the inverting signal input of the amplifier, and a logically low signal (LOW) of the digital output signal is fed back as a second reference voltage (for example VREF−=−1 volt). The reference voltage is converted to a reference current through the resistor between the VREF node and the virtual ground (summing node) at the amplifier input.
In the SC feedback according to prior art (e.g. FIG. 3) a capacitor CREF, is switched using a set of switches between the reference voltage VREF and to the inverting input of the operational amplifier. A reference resistance RREF might be connected on either side of the capacitor to control the time constant of the switching RC circuit. The reference capacitor is charged with the reference voltage (VREF+ or VREF−) corresponding to the digital output bit in a first clock phase, and then transfers a well defined charge packet Q=C*VREF to the integrator in a second clock phase when the switch circuit switches the reference capacitor CREF to the inverting input of the amplifier. The discharge of the capacitor CREF will give an exponentially falling current pulse τ
I=I0*exp(−t/τ) where τ=RREF*CREF is the time constant. Because of the exponentially decreasing pulse shape the charge Q displaced in one clock cycle T varies only slightly when clock jitter occurs, and thus this technique is less sensitive to clock jitter than the ΔΣ ADCs illustrated in FIG. 2.